Method for generating a deep N-well pattern for an integrated circuit design
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United States of America Patent
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Mar 27, 2012
Grant Date -
Dec 17, 2009
app pub date -
Aug 19, 2009
filing date -
Feb 3, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
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