Layout structure of power MOS transistor
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United States of America Patent
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Mar 13, 2012
Grant Date -
Jul 7, 2011
app pub date -
Jan 6, 2010
filing date -
Jan 6, 2010
priority date (Note) -
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Abstract
The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.
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