Apparatus and method for reducing current noise
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United States of America Patent
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Mar 6, 2012
Grant Date -
Sep 29, 2011
app pub date -
Mar 23, 2010
filing date -
Mar 23, 2010
priority date (Note) -
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Abstract
An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.
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