ELECTROLYTIC DEPOSITON AND VIA FILLING IN CORELESS SUBSTRATE PROCESSING
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 6, 2012
Grant Date -
Mar 29, 2012
app pub date -
Sep 25, 2010
filing date -
Sep 25, 2010
priority date (Note) -
Granted
status (Latency Note)
Importance
Abstract
Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.
First Claim
Other Claims data not available
