Gate-length biasing for digital circuit optimization
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United States of America Patent
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Feb 28, 2012
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N/A
app pub date -
Sep 17, 2008
filing date -
May 6, 2005
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Expired
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Abstract
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.
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