Integrated circuit package having reduced interconnects
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United States of America Patent
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Feb 14, 2012
Grant Date -
Jun 17, 2010
app pub date -
Feb 22, 2010
filing date -
Apr 19, 2002
priority date (Note) -
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Abstract
A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
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