System and methods for parametric test time reduction
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 7, 2012
Grant Date -
Jun 24, 2010
app pub date -
Dec 22, 2008
filing date -
Dec 22, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification defining a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method including: computing an estimated maximum test range, at a given confidence level, on a validation set including a subset of the population of semiconductor devices, the estimated maximum test range including the range of values into which all results from performing the test on the set will statistically fall at the given confidence level and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully