Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer
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United States of America Patent
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Feb 7, 2012
Grant Date -
Jul 19, 2007
app pub date -
Jan 5, 2007
filing date -
Jan 18, 2006
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Expired
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Abstract
A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.
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