Method and apparatus for operational-level functional and degradation fault analysis
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United States of America Patent
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Jan 31, 2012
Grant Date -
Oct 6, 2011
app pub date -
Apr 2, 2010
filing date -
Apr 2, 2010
priority date (Note) -
Expired
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Abstract
An apparatus and method are provided for analyzing fault tolerance of a system, and performing “what if?” analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from loss of precision in signal values. The method can detect quality faults, which can allow systems to be built which are resilient to precision losses. Two analysis steps are provided, one static and another simulation-based, which are used in tandem to check the fault tolerance of an automotive or other system. While a simulation-based method checks fault-resilience under specific test cases and fault-scenarios, the static analysis method quickly checks all test cases and fault-scenarios. The static analysis method makes approximations while performing the analysis, and any fault detected is reproduced using the simulation-based method. All analysis operations are performed on operations-level behavioral models of the applications, thereby reducing the cost of analysis.
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