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Abstract

A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first and second estimates of the phase error in a timing signal. A controller receives the first estimate and provides a signal to an NCO. An output from the NCO provides feedback to the error detector to complete a first order feedback loop, providing a first estimate phase error compensation. An integrator receives the second estimate and provides an output estimate for frequency offset of the timing signal that is received by the controller and the sign and magnitude of the integrated phase error are calibrated to provide a frequency offset. The controller determines a number of additional updates to the NCO required to minimize jitter and reduce word-length.

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First Claim