Non-volatile semiconductor memory device comprising capacitive coupling program inhibit circuitry
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United States of America Patent
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Jan 31, 2012
Grant Date -
Aug 7, 2008
app pub date -
Feb 4, 2008
filing date -
Feb 6, 2007
priority date (Note) -
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Abstract
According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.
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