Semiconductor packaging system with stacking and method of manufacturing thereof
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United States of America Patent
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Jan 31, 2012
Grant Date -
Dec 4, 2008
app pub date -
Jun 4, 2007
filing date -
Jun 4, 2007
priority date (Note) -
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Abstract
A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.
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