Balancing NFET and PFET performance using straining layers
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United States of America Patent
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Jan 31, 2012
Grant Date -
Jul 14, 2011
app pub date -
Jan 14, 2010
filing date -
Jan 14, 2010
priority date (Note) -
Expired
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Abstract
An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
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