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Abstract

I.sup.2C clock generators are implemented using a variety of methods. Using one such method, a method is implemented using logic circuitry arranged in a state machine to control the clock signal (110) on the I.sup.2C bus. A first state (202) of the state machine determines whether to effect a clock stretching delay. A second state (206) of the state machine determines whether the I.sup.2C bus is configured to run in a standard clock mode or in another one of multiple faster clock modes. A third state (210) of the state machine drives the clock signal in one binary logic state for more than about 0.5 microseconds before allowing the clock signal (110) to be driven in the other binary logic state and allowing the clock signal to remain in the other binary logic state for more than about 0.5 microseconds.

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First Claim