Power management for buses in cmos circuits
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United States of America Patent
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Jan 17, 2012
Grant Date -
Oct 16, 2008
app pub date -
Sep 11, 2006
filing date -
Sep 12, 2005
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Abstract
The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state (42; 52) of that said circuit wherein all of its own control and messaging signals are taken to their zero level. The present invention claimed relates to the methodology of entering said circuit into this pre-determined state (42;52); where all said signal and messaging lines are taken to zero; thereby reducing power consumption within an electronic circuit when its status is defined as being shut-down or standby.
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