Flip chip semiconductor package and fabrication method thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8093721
SERIAL NO

12438362

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Abstract

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There is provide a flip chip semiconductor package comprising: an electrode pad formed a semiconductor substrate; a lower metal bonding layer formed on the electrode pad; an upper metal bonding layer formed on the lower metal bonding layer and having a post shape of a predetermined height; and a conductive bump formed on the upper metal bonding layer, and a solder bump covers at least partially the surface of the upper metal bonding layer. An insulating layer for electrode reconfiguration is formed around the electrode pad on the substrate, and the insulating layer has a predetermined thickness to prevent the penetration of α particles from the solder bump. The semiconductor package may further comprise an oxidation preventing layer between the solder bump and the upper metal bonding layer. In accordance with the present invention, there is realized the flip chip semiconductor package which improves the adhesive strength of the solder bump and which more improves the reliability in the flip chip bump structure of fine pitches.

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Patent Owner(s)

Patent OwnerAddress
NEPES CORPORATION654-2 GAK-RI OCHANG-MYUN CHEONGWON-GUN CHUNGBUK 363-883

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kang, In-Soo Chungbuk, KR 3 42
Park, Byung-Jin Chungbuk, KR 3 44

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