Power aware asynchronous circuits

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8086975
APP PUB NO 20090288058A1
SERIAL NO

12421963

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
UNIVERSITY OF SOUTHERN CALIFORNIA1150 SOUTH OLIVE STREET LOS ANGELES CA 90015

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beerel, Peter A Encino, US 14 225
Lines, Andrew Malibu, US 25 652
Saifhashemi, Arash Los Angeles, US 1 34
Shiring, Ken Campbell, US 1 34

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation