Memory circuit for display panel driving and driving method thereof
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 20, 2011
Grant Date -
Jun 5, 2008
app pub date -
Sep 4, 2003
filing date -
Jun 23, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Provided is a circuit driving method which can minimize a problem generated by a peak current in a display memory device. Data to be transferred to a display panel is read out from a memory cell array storing binary information. The read-out data are stored in source data buffers and a plurality of source data buffers are divided into several groups and then enabled. An enable signal for each group is derived from a single enable signal and has a different delay time. In the source data buffers delayed by each group and enabled, consumption of current is distributed so that a peak current flowing in the overall source data buffer is lowered. Thus, reliability in the operation of a circuit is improved and the operation speed increases.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully