High performance data rate system for flash devices
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United States of America Patent
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Nov 29, 2011
Grant Date -
Jul 28, 2011
app pub date -
Sep 3, 2009
filing date -
Dec 1, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.
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