Digital phase-locked loop operating based on fractional input and output phases
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United States of America Patent
Stats
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Oct 25, 2011
Grant Date -
Jun 4, 2009
app pub date -
Nov 29, 2007
filing date -
Nov 29, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping track of the number of oscillator signal cycles based on the reference signal.
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