Chip packaging with metal frame pin grid array
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United States of America Patent
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Oct 11, 2011
Grant Date -
Jul 21, 2011
app pub date -
Jun 8, 2009
filing date -
Dec 6, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.
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