Timing analysis apparatus and method for semiconductor integrated circuit in consideration of power supply and ground noises
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United States of America Patent
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Sep 13, 2011
Grant Date -
Apr 23, 2009
app pub date -
Oct 20, 2008
filing date -
Oct 19, 2007
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Expired
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Abstract
In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.
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