Semiconductor chip with seal ring and sacrificial corner pattern
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Sep 13, 2011
Grant Date -
Jul 30, 2009
app pub date -
Mar 24, 2009
filing date -
Sep 10, 2004
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
First Claim
Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
ACACIA RESEARCH GROUP LLC | 767 3RD AVE 6TH FLOOR NEW YORK NY 10017 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Furusawa, Takeshi | Tokyo, JP | 60 | 732 |
# of filed Patents : 60 Total Citations : 732 | |||
Goto, Kinya | Tokyo, JP | 20 | 152 |
# of filed Patents : 20 Total Citations : 152 | |||
Matsuura, Masazumi | Tokyo, JP | 45 | 973 |
# of filed Patents : 45 Total Citations : 973 | |||
Miura, Noriko | Tokyo, JP | 26 | 176 |
# of filed Patents : 26 Total Citations : 176 |
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Patent Citation Ranking
- 4 Citation Count
- H01L Class
- 3.01 % this patent is cited more than
- 14 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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