Method of generating test condition for detecting delay faults in semiconductor integrated circuit and apparatus for generating the same
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United States of America Patent
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Aug 23, 2011
Grant Date -
Nov 19, 2009
app pub date -
May 15, 2009
filing date -
May 16, 2008
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Abstract
Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.
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