Semiconductor device and manufacturing method thereof
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Aug 23, 2011
Grant Date -
Aug 9, 2007
app pub date -
Aug 9, 2006
filing date -
Aug 10, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of manufacturing a semiconductor device 28 in which a plating mask 38, 39 having a noble metal plating layer 35 as an uppermost layer is formed at a predetermined portion on an obverse surface side or a reverse surface side of a leadframe material 10, and the leadframe material 10 is consecutively subjected to etching by using the plating mask 38, 39 as a resist mask, so as to form external connection terminal portions 22 which electrically communicate with a semiconductor element 18 disposed in an interior of an encapsulating resin 21, and which project downwardly. Base metal plating or noble metal plating 33 exhibiting etching solution resistance is provided as a lowermost layer of the plating mask 38, 39.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
MITSUI HIGH-TEC INC | 10-1 KOMINE 2-CHOME YAHATANISHI-KU KITAKYUSHU-SHI FUKUOKA 807-8588 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Hirashima, Tetsuyuki | Fukuoka, JP | 2 | 63 |
# of filed Patents : 2 Total Citations : 63 | |||
Takai, Keiji | Fukuoka, JP | 7 | 257 |
# of filed Patents : 7 Total Citations : 257 |
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Patent Citation Ranking
- 2 Citation Count
- H01L Class
- 3.01 % this patent is cited more than
- 14 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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