bacterium strain capable of decomposing/volume-reducing plant residue
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United States of America Patent
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Aug 23, 2011
Grant Date -
Feb 4, 2010
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Sep 21, 2007
filing date -
Oct 4, 2006
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Abstract
KS-C4 strain (FERM BP-10842) that is capable of decomposing a plant residue and reducing a volume of the plant residue or a culture of the cell is added to a plant residue.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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SDS BIOTECH K K | 3 KANDA-NERIBEICHO CHIYODA-KU TOKYO 1010022 ?1010022 |
International Classification(s)

- 2007 Application Filing Year
- C12S Class
- 15 Applications Filed
- 5 Patents Issued To-Date
- 33.34 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Kawabata, Takahiro | Sodegaura, JP | 8 | 53 |
# of filed Patents : 8 Total Citations : 53 |
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- 0 Citation Count
- C12S Class
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- 14 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
US Patent No: 5751012
Polysilicon pillar diode for use in a non-volatile memory cell
Abstract
There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digitline. The memory element is disposed in series with the diode, also between the wordline and the digitline. The diode is capable of delivering the large current flow required to program the memory element without also requiring the surface space on the upper surface of the memory matrix normally associated with such powerful diodes. The invention allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix. Further, the memory cell is easily fabricated using standard processing techniques. The unique layout of the inventive memory cell allows fabrication with as few as three mask steps or less.
Description
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Legal Events
Date | Code | Event | Description |
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Dec 23, 2009 | AS | ASSIGNMENT | free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK Effective Date: Dec 23, 2009 free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK Effective Date: Dec 23, 2009 |
Oct 14, 2009 | FPAY | FEE PAYMENT | year of fee payment: 12 |
Oct 24, 2005 | FPAY | FEE PAYMENT | year of fee payment: 8 |
Sep 27, 2001 | FPAY | FEE PAYMENT | year of fee payment: 4 |
May 12, 1998 | I | Issuance | |
Apr 30, 1998 | STCF | INFORMATION ON STATUS: PATENT GRANT | free format text: PATENTED CASE |
Dec 05, 1997 | FEPP | FEE PAYMENT PROCEDURE | free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
Sep 27, 1995 | AS | ASSIGNMENT | free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WOLSTENHOLME, GRAHAM R.;IRELAND, PHILIP J.;REEL/FRAME:007713/0737;SIGNING DATES FROM 19950814 TO 19950908 Owner name: MICRON TECHNOLOGY, INC., IDAHO |
Jun 07, 1995 | F | Filing | |
Jun 07, 1995 | PD | Priority Date |

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