Semiconductor devices including semiconductor dice in laterally offset stacked arrangement
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United States of America Patent
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Aug 16, 2011
Grant Date -
Jun 17, 2010
app pub date -
Feb 22, 2010
filing date -
Jun 21, 2001
priority date (Note) -
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Abstract
A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device.
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