Semiconductor memory
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United States of America Patent
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Jul 12, 2011
Grant Date -
Jan 14, 2010
app pub date -
Sep 15, 2009
filing date -
Mar 19, 2007
priority date (Note) -
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Abstract
Dummy memory cells are disposed on an outside of real memory cells positioned on a peripheral part of a matrix. First contacts coupling between two wiring layers laminated on a semiconductor substrate are disposed around each of the real and dummy memory cells, and are shared by an adjacent real or dummy memory cell. Number of the first contacts disposed in each of the dummy memory cells is set to be smaller than number of the first contacts disposed in each of the real memory cells. Accordingly, even when a well region is not formed normally due to a variation in manufacturing conditions, it is possible to prevent an abnormal power supply current from being flown into the dummy memory cells, and an occurrence of latch up can be prevented.
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