Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
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United States of America Patent
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Jul 12, 2011
Grant Date -
Nov 19, 2009
app pub date -
Aug 28, 2006
filing date -
Dec 2, 2005
priority date (Note) -
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Abstract
A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.
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