Input stage for mixed-voltage-tolerant buffer with reduced leakage
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United States of America Patent
Stats
-
Jun 28, 2011
Grant Date -
Aug 6, 2009
app pub date -
Mar 16, 2009
filing date -
Nov 20, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.
First Claim
Other Claims data not available
