Method and apparatus for a zero voltage processor sleep state
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United States of America Patent
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May 31, 2011
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N/A
app pub date -
Nov 8, 2007
filing date -
Dec 30, 2005
priority date (Note) -
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Abstract
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.
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International Classification(s)
- H02J:CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR D....
- H02M:APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEE....
- G06F:ELECTRIC DIGITAL DATA PROCESSING
- F02P:IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INT....
- G11C:STATIC STORES
- G01F:MEASURING VOLUME, VOLUME FLOW, MASS FLOW, OR LIQUI....
- H02H:EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
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