Optimum power management of system on chip based on tiered states of operation
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United States of America Patent
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May 10, 2011
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app pub date -
May 9, 2007
filing date -
May 9, 2007
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Abstract
Optimum power management of system on chip based on tiered states of operation is disclosed. In one embodiment, a system on chip includes a hardware module including one or more of a microcontroller, a microprocessor, a DSP core, a memory, a timing source, a peripheral, and an external interface to have a real time counter module of the peripheral isolated from a rest of the hardware module using a plurality of voltage level shifting cells and/or a plurality of voltage island cells. Also, the system on chip includes a software module associated with the real time counter module to generate one or more control signals to one or more devices external to the system on chip during a sleep mode of the system on chip.
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