Family

Loading Family data...

• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
GRACO CHILDREN'S PRODUCTS INC	3 GLENLAKE PARKWAY ATLANTA GA 30328

International Classification(s)

• A63G:MERRY-GO-ROUNDS; SWINGS; ROCKING-HORSES

• 2007 Application Filing Year
• A63G Class
• 57 Applications Filed
• 37 Patents Issued To-Date
• 64.92 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Bellows, William B	Wyomssing, US	47	853
# of filed Patents : 47 Total Citations : 853
Clapper, Joshua E	Exeter, US	44	648
# of filed Patents : 44 Total Citations : 648
Papageorge, Nick Efthemios	Upper Darby, US	2	44
# of filed Patents : 2 Total Citations : 44

Cited Art Landscape

Load Citation

• No Cited Art to Display

Loading Cited Art Landscape...

Patent Citation Ranking

• 21 Citation Count
• A63G Class

• 76.83 % this patent is cited more than
• 14 Age

Forward Cite Landscape

Load Citation

• No Forward Cites to Display

Loading Forward Cite Landscape...

Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 10, 2011	US,7938731,B2   US7938731B2	GRANTED PATENT AS SECOND PUBLICATION
June 12, 2008	US,20080136229,A1   US20080136229A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 4892836

Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices

---

Abstract

---

This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

---

 

---

Description

---

Claims

---

Claims data not available

---

Legal Events

 

• FPAY2001
• FPAY1997
• FPAY1993
• I1990
• STCF1989
• F1987
• AS1987
• PD1986

Date	Code	Event	Description
Jun 21, 2001	FPAY	FEE PAYMENT	year of fee payment: 12
Jun 26, 1997	FPAY	FEE PAYMENT	year of fee payment: 8
Jun 24, 1993	FPAY	FEE PAYMENT	year of fee payment: 4
Jan 09, 1990	I	Issuance
Nov 06, 1989	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Mar 23, 1987	F	Filing
Mar 10, 1987	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ANDREINI, ANTONIO;CONTIERO, CLAUDIO;GALBIATI, PAOLA;REEL/FRAME:004695/0110 Owner name: SGS MICROELETTRONICA S.P.A., STRADALE PRIMSOLE 50 Effective Date: Mar 10, 1987
Mar 27, 1986	PD	Priority Date