Packet fragment reassembly
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United States of America Patent
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May 3, 2011
Grant Date -
Sep 2, 2010
app pub date -
Feb 27, 2009
filing date -
Feb 27, 2009
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Abstract
An apparatus for packet fragment reassembly includes a memory and a fragment processing block coupled to the memory. The memory caches information contained in the headers of a plurality of packet fragments, wherein the plurality of packet fragments are identified as belonging to a particular packet. The fragment processing block directly performs operations to each packet fragment according to the information cached in the memory and a predetermined standard, wherein the information cached in the memory is used to track whether all packet fragments associated with the particular packet have been received at the apparatus.
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