Method and system to access memory

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United States of America Patent

PATENT NO 7929356
SERIAL NO

12205518

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Abstract

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This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

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Patent Owner(s)

Patent OwnerAddress
ARTEMIS ACQUISITION LLC801 CALIFORNIA ST MOUNTAIN VIEW CA 94041

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
De, Caro Richard V El Dorado Hills, US 6 85
Manea, Danut Saratoga, US 17 113

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