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Abstract

A method optimizes a DSP Input clock using a clock comparing/analyzing circuit. The method of the present invention enables PLD to select a delay function of the PLD and signals from a plurality of patterns, in addition to varying three elements' values of R, L and C, a driver delay, and a characteristic change by peripheral elements of patterns that a clock passes to thereby obtain an optimal characteristic. Particularly, the inventive method provides an optimal clock with the best performance among clocks from the pattern. This method has the following two functions: (1) allowing the paths from a plurality of patterns to be scanned individually and a pattern having the lowest noise level to be searched; (2) searching the maximum SNR(Signal to Noise) value by providing a delay offset to an optimal path having the lowest noise level which is searched from the first function, and wherein an optimal path is searched and connected by checking the operation periodically by a timer to provide optimal characteristics in case peripheral environments change.

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First Claim