Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

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United States of America Patent

PATENT NO 7915107
APP PUB NO 20090311837A1
SERIAL NO

12492320

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Abstract

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This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

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Patent Owner(s)

  • MIE FUJITSU SEMICONDUCTOR LIMITED;SUVOLTA, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kapoor, Ashok K Palo Alto, US 101 3596

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