Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers
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United States of America Patent
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Mar 22, 2011
Grant Date -
Jan 1, 2009
app pub date -
Sep 12, 2008
filing date -
Feb 11, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
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