Wafer level system in package and fabrication method thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7906842
SERIAL NO

11828741

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Abstract

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There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.

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Patent Owner(s)

Patent OwnerAddress
NEPES CORPORATION654-2 GAK-RI OCHANG-MYUN CHEONGWON-GUN CHUNGBUK 363-883

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Park, Yun Mook Cheongju-Si, KR 6 183

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