Method and apparatus for scheduling test vectors in a multiple core integrated circuit
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United States of America Patent
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Mar 8, 2011
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Mar 19, 2009
app pub date -
Sep 14, 2007
filing date -
Sep 14, 2007
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Abstract
A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.
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