Resolving metastability
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Feb 1, 2011
Grant Date -
Sep 9, 2010
app pub date -
Feb 26, 2010
filing date -
Mar 3, 2009
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level.
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