Capacitors with low equivalent series resistance
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United States of America Patent
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Jan 4, 2011
Grant Date -
Jul 2, 2009
app pub date -
Sep 5, 2007
filing date -
Sep 6, 2006
priority date (Note) -
Expired
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Abstract
An electric double layer capacitor (EDLC) in a coin or button cell configuration having low equivalent series resistance (ESR). The capacitor comprises mesh or other porous metal that is attached via conducting adhesive to one or both the current collectors. The mesh is embedded into the surface of the adjacent electrode, thereby reducing the interfacial resistance between the electrode and the current collector, thus reducing the ESR of the capacitor.
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