MEMS device with integrated via and spacer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 4, 2011
Issued Date -
N/A
app pub date -
Feb 25, 2009
filing date -
Feb 25, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A MEMS device and fabrication method are disclosed. A bottom substrate having an insulating layer sandwiched between an upper layer and a lower layer may be bonded to a device layer. One or more portions of the upper layer may be selectively removed to form one or more device cavities. Conductive vias may be formed through the lower layer at locations that underlie the one or more device cavities and electrically isolated from the lower layer. Devices may be formed from the device layer. Each device overlies a corresponding device cavity. Each device may be connected to the rest of the device layer by one or more corresponding hinges formed from the device layer. One or more electrical contacts may be formed on a back side of the lower layer. Each contact is electrically connected to a corresponding conductive via.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully