Semiconductor device
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United States of America Patent
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Jan 4, 2011
Issued Date -
N/A
app pub date -
Dec 20, 2006
filing date -
Dec 22, 2005
priority date (Note) -
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Abstract
For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE | 586-9 USHIGAFUCHI AKATSUKA TSUKUBA-CITY IBARAKI PREFECTURE 305-0062 | |
TOHOKU UNIVERSITY | MIYAGI PREFECTURE JAPAN MIYAGI |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Ohmi, Tadahiro | Miyagi, JP | 798 | 14083 |
Teramoto, Akinobu | Miyagi, JP | 114 | 811 |
Watanabe, Kazufumi | Miyagi, JP | 71 | 1032 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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