Semiconductor device

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United States of America Patent

PATENT NO 7863713
SERIAL NO

12086886

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Abstract

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For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.

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Patent Owner(s)

Patent OwnerAddress
FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE586-9 USHIGAFUCHI AKATSUKA TSUKUBA-CITY IBARAKI PREFECTURE 305-0062
TOHOKU UNIVERSITYMIYAGI PREFECTURE JAPAN MIYAGI

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ohmi, Tadahiro Miyagi, JP 798 14083
Teramoto, Akinobu Miyagi, JP 114 811
Watanabe, Kazufumi Miyagi, JP 71 1032

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