Low jitter CMOS to CML converter
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United States of America Patent
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Dec 7, 2010
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app pub date -
Feb 23, 2009
filing date -
Feb 22, 2008
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Abstract
The present invention provides a low jitter CMOS to CML converter, including: a differential circuit including differential pair transistors, a pair of loads and a biased transistor, each differential transistor of the differential pair transistors having an input terminal, an output terminal and a connection terminal. With the current compensation device, an additional current path may be provided for the current of the biased transistor which is used as a constant current source when the differential transistors are turned off, so that the peak tail current in the biased transistor current may be eliminated. Thus, the problem caused by the tail current that the common mode output voltages of the converter is unstable and has a high jitter may be solved.
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