Semiconductor device with multiple transistors formed in a partially depleted semiconductor-on-insulator substrate
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United States of America Patent
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Dec 7, 2010
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N/A
app pub date -
Feb 6, 2009
filing date -
Feb 6, 2009
priority date (Note) -
Expired
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Abstract
A semiconductor device comprises a partially depleted semiconductor-on-insulator structure having both a three terminal JFET and a four terminal JFET constructed thereon. The four terminal JFET comprises a source region, a drain region, a channel region, a front gate region, and a back gate region formed in a semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET comprises a source region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure, and a drain region spaced apart from the source region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET further comprises a channel region between the source region and the drain region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET also comprises a gate region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. A gate-to-channel junction of the three terminal JFET is formed deep enough in the semiconductor layer such that the channel region of the three terminal JFET abuts an insulating layer of the semiconductor-on-insulator structure.
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