Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
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Nov 30, 2010
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Nov 19, 2007
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Oct 21, 2002
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Abstract
An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R.sub.12.
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