Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom
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United States of America Patent
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Nov 30, 2010
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N/A
app pub date -
Sep 18, 2008
filing date -
Sep 18, 2008
priority date (Note) -
Expired
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Abstract
A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.
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