Non-volatile programmable memory cell and array for programmable logic array
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United States of America Patent
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Nov 23, 2010
Grant Date -
Jul 17, 2008
app pub date -
Mar 25, 2008
filing date -
Jun 13, 2005
priority date (Note) -
Expired
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Abstract
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
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