Task concurrency management design method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7831951
SERIAL NO

11761275

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Abstract

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A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.

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Patent Owner(s)

Patent OwnerAddress
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)KAPELDREEF 75 3001 LEUVEN
KATHOLIEKE UNIVERSITEIT LEUVENWAAISTRAAT 6 BUX 5105 LEUVEN B-3000
UNIVERSITY OF PATRAS26504 RION PATRA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Catthoor, Francky Temse, BE 72 1709
Cossement, Nathalie Rekkem, BE 2 97
Lauwereins, Rudy Winksele, BE 2 97
Marchal, Paul Blanden, DE 27 698
Prayati, Aggeliki Athens, GR 2 97
Wong, Chun Leuven, BE 3 99
Yang, Peng Leuven, BE 169 590

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